The number of gates in the original truth table of the arithmetic and logic unit, before the AND and OR gates simplification, is almost equivalent to the memory unit. The two inputs of the original truth table are used as the 2D address of the memory module to store the output. After the address is read, it is equivalent to two inputs and one output. This is the so-called "memory operator". For a single fixed function operator, it is impossible to use this method to consume the largest number of gates without simplification; for a large number of fixed operators, the complexity of virtual wiring among operators that can only be fixedly placed consumes more memory units than those that can be rewritten and freely placed to reduce the complexity of virtual wiring. So, it is cost-effective.
The other method of content addressing, rather than the numerical decoder addressing, is to use a comparison gate array to compare the content with the input to locate and access the adjacent content. When the number of units is large enough, the number of gates consumed by the numerical address decoder exceeds the number of gates consumed by the parallel content comparison. The numerical address decoding method can only determine one address, and the content comparison method can have multiple connections. For dynamic logic operations, "memory and computation in one" is more cost-effective. Operators and operands in traditional neural networks are fixed side by side without addressing problems; a dynamic neural network with dynamic connections among neurons that change frequently, instead of being fixed, is more suitable for this approach.
Of course, the ultimate "memory and computation in one" is that the semiconductor itself is a non-volatile memory, instead of adding another memory side by it to remember the switch state.
Comparing the XOR/AND gate array consumption of the symbolic matcher and the AND/OR gate consumption of the numerical address decoder: the former has more gates per unit but the gates per unit are the same and the gates will not increase as the number of units increases; the latter will increase the gates as the number of units increases. The more gates there are, the more direct impact is that the time consumed from input to output becomes slower as the number of units increases.
回复删除When the number of netlist switches consumed by the multiple-to-multiple dynamic connection among ALUs and REGs is greater than the Karnaugh map simplification of actual operator (ALU), the virtual operator (memory operator) consumes less on the contrary. Compare to fixed actual operators, virtual operators can dynamically change positions to minimize the number of netlist switches consumed by dynamic connection.
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