Sense reactor

There is no more processor

There is a reactor

The reactor I talked about is not the power supply for the processor; it is to replace the processor.

I even had my own Neuron chip replaced by my own Sense reactor. I didn’t “give up halfway”; I was iterated upon by myself.

Biological neurons are  subset

Particle reactions are  global set

My system logic design is based entirely on the presupposed magnetic switch element

The graph traveling: the traditional way is addition and multiplication of the address number; the new way is the switch shifting on the array. 

A program is segments of collection or class graph traveling until blank or separator.

One way is to dynamically connect the results of each traveling by their association behaviour definitions to wait for value input to start the computation to output and then the connection perhaps be modified or released after each computation, but this way will consume so many dynamic allocated buses and switches for netlist.

The other way is to directly replace the series of traveling results by their synonym definitions as computation.

Virtual operator

The number of gates in the original truth table of the arithmetic and logic unit, before the AND and OR gates simplification, is almost equivalent to the memory unit. The two inputs of the original truth table are used as the 2D address of the memory module to store the output. After the address is read, it is equivalent to two inputs and one output. This is the so-called "memory operator". For a single fixed function operator, it is impossible to use this method to consume the largest number of gates without simplification; for a large number of fixed operators, the complexity of virtual wiring among operators that can only be fixedly placed consumes more memory units than those that can be rewritten and freely placed to reduce the complexity of virtual wiring. So, it is cost-effective.

The other method of content addressing, rather than the numerical decoder addressing, is to use a comparison gate array to compare the content with the input to locate and access the adjacent content. When the number of units is large enough, the number of gates consumed by the numerical address decoder exceeds the number of gates consumed by the parallel content comparison. The numerical address decoding method can only determine one address, and the content comparison method can have multiple connections. For dynamic logic operations, "memory and computation in one" is more cost-effective. Operators and operands in traditional neural networks are fixed side by side without addressing problems; a dynamic neural network with dynamic connections among neurons that change frequently, instead of being fixed, is more suitable for this approach.

Of course, the ultimate "memory and computation in one" is that the semiconductor itself is a non-volatile memory, instead of adding another memory side by it to remember the switch state.

The dynamic logic model

The basis of an operation system is the connection among operands and operators. The connection state is specified sequentially by instruction codes, it is called control-driven. The next connection state is generated by the result of the operation, it is called reaction-driven. The operation starts when the operands change, it is called data/event-driven. The operation including connection changing for the formula automatically solving starts when any operand is unknown, it is called goal-driven. Reaction-driven is also data/event-driven and goal-driven, but control-driven is not. 

The dynamic logic model is reaction-driven instead of control-driven. 

Ĉu projekcii altajn dimensiojn al malaltaj dimensioj kaj sintezi altajn dimensiojn de malaltaj dimensioj povas esti funkciigitaj per la sama integra cirkvito?

Could the operands, virtual operators, and virtual wires be uniformed to be only one kind of unit?

With the number decoder addressing, the virtual operator assignment is to assign the output matrix.

With the direct symbol referring, the virtual operator assignment is to assign the pairs of input and output.

In the traditional processor, the function is a program counter assignment to jump to the function body and return with the parameters pushed in and popped out the stack.

In the sense graph processor, regard the traditional function declaration and definition as the same type of interreplaceable sentence, use the symbol ≡ to link all interreplaceable sentences, and choose the suitable one according to the configurable situation on site, so the function can be redefined during runtime.

The Graph Machine

The traditional computer mechanism is that a central processing unit processes documents in a memory module just like a person is reading and writing a document; the graph machine is that the words in the documents in the memory module are contacting to react with each other automatically by themselves via the switches network, and there is no such one processing the document. Verbs, conjunctions, and prepositions are operators; nouns, adjectives, adverbs, articles, and quantifiers are operands. Just be like the contact reaction of particles. 

Operators (arithmetic logic units) and links (wires) in the application specific integrated circuit are like fixed houses and roads in the city; blocks and virtual wires in the field programmable gate array are like fixed houses and variable roads; what would it be called if virtual operators and virtual links inside are like variable houses and roads?

In fact, the arithmetic logic unit before cost down is equivalent to a memory module, which is removed the redundant gates for fixed purposes. However, fixedly placed arithmetic logic units will cause virtual wires consuming more time and space than the original memory module, so it is better to use the replaceable virtual operators to replace the fixed ones.

Of course, the best is that the switch gatecon itself is a non-volatile memory.

La "ŝaltilo = memoro" bazita sistemdezajno tute malsama de la antaŭa dezajno estis en preparado, 

nur atendante por unu tago tia "ŝaltilo = memoro" baza komponento povas esti uzata.

De simulado de la rekta konduto de la cirkvito neefike per la instrukcia kodprogramo de la instrukciaĵaro arkitekturprocesoro ĝis simulado de la partiklo kontaktanta reagon malefike per la integra cirkvito.

sen

aŭtoj sen radoj 

aviadiloj sen surteriĝo

uzantinterfaco sen redaktilo

procesoro sen programkalkulilo

早期设计是在开关网络旁摆一块将输入的 sentences 与 senses 匹配解译成开关网络连接状态与将开关网络连接状态及其连接的 senses 编译成 sentences 输出的功能线路仅有一对 ports，后来进阶到内部开关网络动态连接的 senses 之间也相互对彼此收发 sentences 于是就将其合併至开关网络成为匹配开关网络，这么一来，不仅只有一种 port 而且连同 conversation 也和跨芯片开关网络连接端口一样是多 ports。除此之外，原本用于芯片间交互缓存（当 travel 到一个 sense 是 uncached 即透过缓存端口 send 一个自己至自身所记载本尊所在芯片然后彼端传回一串本尊的 subsenses 接到这个 sense 变成 cached）回存（当一个 sense 有增删 subsense 或有更新也就是删掉旧的 subsense 增加新的 subsense 即透过「回存+」或「回存-」端口 send 一个自己后接一串增或删的 subsenses 至其本身记载所有本尊与分身所在芯片去接上为那 sense 的 subsenses 或比对 subsenses 将之删除）的 ports 亦与之合併改成以 sentences 实现 sense graphs 缓存与回存的操作，然而 sentence 是定义结构可弹性扩充的所以还要设法由内部结构而非外部检查的方式避免 injection 破坏基底缓存回存的机制。

非淘汰传统处理器换成图论机不可

匹配开关网络当配置量足夠时即配置成并行、不夠时则配置成串行，弹性变动带宽乃图论机之基本。传统处理器改一下也可以串行处理不固定长短的数据，增加内存模组再外套解码器所增加的位址长度在处理器端固定带宽的定址输出端口可改成串行输出再并分到内存模组位址解码器的输入端口，而定到址的内容也可以位移串行输出至处理器端，所以非淘汰传统处理器换成图论机不可的原因并不是不固定长短数据的定址与运算。当内存模组扩充到某个程度的量后，定址解码器所占空间开始超过匹配开关网络状态内存所占空间，花了那么多空间仅定了一个址相对于开关网络可同时多对多连接当然是划不来了，这才是非淘汰传统处理器换成图论机不可的原因之一。将独立内存模组的定址解码线路改成内容匹配线路，由串行输入位移比对到内容相符的槽起始位移串行输出给处理器所耗的空间就和开关网络的匹配线路一样，但仅一对串行端口就是效能瓶颈，所以非淘汰传统处理器换成图论机不可。

The travelers in the graph processor

The new graph processor uses the travelers to replace the program counters in the old sequential processor. 

The travelers in the graph machine are not the address registers in the old sequential processor, they are the node markers shifting through the switches network.

The ports of the Sense Graph chip

There are two basic interfaces among the Sense Graph chips:

1. sentences stream conversation port 

2. data flow channel ports connecting the switches network across chips 

Compare with the memory address output port and the instruction / data port of the traditional stack processor.

Graph machine & Replacement machine

Graph machine 是模拟人在阅读或算式的过程是先同时看到几个重要关键的字符再系结旁边的字符组成认知图而理解一段文式然后进行思考。

Replacement machine 是模拟人在阅读或算式的过程会逐步将文式片段转换成自己已理解的片段，多次返复代换到最后其实就是结果与答案了。

Graph machine & Replacement machine

Graph machine 基本是依结合优先顺序透过 comparation gate array 同时并行位移比对将 match 到多个 Sense 中取左边第一个连接到动态配置的 virtual wire 上，之后 sense 欲变更 virtual wire 的连接状态亦是相同的方式输出 senses 到 comparation gate array 上。

Replacement machine 基本透过 comparation gate array 与 replacement table 做同时并行位移比对将 match 到的片段 replace，返复进行至没有任何 match 了即为运算完成。排在 table 前面的优先 replace 即达 graph machine 中结合力较强的 operator 优先结合的效果，过程中遇到 definition keyword 就将片段加入 table 或从其刪除。

两者对括号的处理方式都是在比对到左括号时都暂不 connect 或 replace ，后面再一并进行消括号的动作，自多个左括号处同时并行向右位移比对出右括号，左右括号间仅存在一 Sense 即消掉左右括号，接着再重复前面的动作 loop 至不再比对出任何括号，若自左括号处向右位移比对到左括号则什么都不做、等待下一 loop 后面再重复进行一次。

Graph machine 是接线生的角色，接完线后 graph 自己是线路、自己在动；Replacement machine 的 senses 则完全是被动处理，纯粹是 data。

Can these two machines be combined to be one machine?